Bit error testing and training in double data rate (DDR) memory system

摘要

DDR PHY interface bit error testing and training is provided for Double Data Rate memory systems. An integrated circuit comprises a bit error test (BERT) controller that provides a bit pattern; and a physical interface having a plurality of byte lanes. A first byte lane is connected by a loopback path to a second byte lane and the BERT controller writes the bit pattern that is obtained using the loopback path to evaluate the physical interface. The evaluation comprises (i) a verification that the bit pattern was properly written and read; (ii) a gate training process to position an internal gate signal; (iii) a read leveling training process to position both edges of a strobe signal; and/or (iv) a write bit de-skew training process to align a plurality of bits within a given byte lane.

主权项

1. An integrated circuit, comprising:
a bit error test controller that provides a bit pattern; and a physical interface having a plurality of byte lanes, wherein said physical interface converts digital signals from the bit error test controller into waveforms for one or more memory devices, wherein at least a first byte lane is connected by a loopback path to a second byte lane and wherein said bit error test controller provides said bit pattern using a write operation that is then obtained using said loopback path to evaluate said physical interface based on said bit pattern.