Canary circuit with passgate transistor variation

摘要

A canary circuit with passgate transistor variation is described herein. The canary circuit includes a memory canary circuit that has a plurality of bitcells. Each bitcell has at least a passgate transistor that is driven by a wordline voltage. The canary circuit further includes a regulator circuit that outputs a wordline voltage that accounts for a predetermined offset of a threshold voltage of the passgate transistor. In an embodiment, the regulator circuit is a subtractor circuit that generates the wordline voltage from a reference voltage based in part on the threshold voltage variation of the passgate transistor.

主权项

1. An apparatus, comprising:
a memory canary circuit including a plurality of bitcells, each bitcell having at least one passgate transistor; a regulator circuit configured to output a wordline voltage that accounts for a predetermined offset from a threshold voltage of the passgate transistor, wherein the passgate transistor is driven by the wordline voltage; and a test circuit configured to determine memory canary circuit failure on a condition that a number of read/write errors on the memory canary circuit exceed a predetermined threshold, wherein an operating frequency and voltage are altered based on the memory canary circuit failure determination.