发明名称 |
Semiconductor memory having volatile and multi-bit non-volatile functionality and method of operating |
摘要 |
A semiconductor memory cell, semiconductor memory devices comprising a plurality of the semiconductor memory cells, and methods of using the semiconductor memory cell and devices are described. A semiconductor memory cell includes a substrate having a first conductivity type; a first region embedded in the substrate at a first location of the substrate and having a second conductivity type; a second region embedded in the substrate at a second location of the substrate and have the second conductivity type, such that at least a portion of the substrate having the first conductivity type is located between the first and second locations and functions as a floating body to store data in volatile memory; a trapping layer positioned in between the first and second locations and above a surface of the substrate; the trapping layer comprising first and second storage locations being configured to store data as nonvolatile memory independently of one another; and a control gate positioned above the trapping layer. |
申请公布号 |
US9257179(B2) |
申请公布日期 |
2016.02.09 |
申请号 |
US201414549322 |
申请日期 |
2014.11.20 |
申请人 |
Zeno Semiconductor, Inc. |
发明人 |
Widjaja Yuniarto |
分类号 |
G11C14/00;H01L27/105;H01L27/108;H01L27/115;H01L29/78;G11C16/04 |
主分类号 |
G11C14/00 |
代理机构 |
Law Office of Alan W. Cannon |
代理人 |
Cannon Alan W.;Law Office of Alan W. Cannon |
主权项 |
1. A method of operating a memory cell having a floating body for storing, reading, and writing data as volatile memory, and a trapping layer comprising two storage locations for storing data as non-volatile memory, the method comprising:
storing permanent data in one of said two storage locations in the trapping layer; storing additional data to the floating body while power is applied to the memory cell; and transferring the additional data stored in the floating body to the other of said two storage locations of the trapping layer as non-volatile memory when power to the cell is interrupted; wherein when said volatile memory cell is in a first state, electrons are injected into said trapping layer and when said volatile memory cell is in a second state, no electrons are injected into said trapping layer. |
地址 |
Cupertino CA US |