Semiconductor integrated circuit including a state machine

摘要

A state machine; a BIST circuit including a test pattern generator and an expected value comparison circuit; a state monitoring circuit configured to monitor whether or not a state of the state machine is a specific state; and a transition request detection circuit configured to detect a transition request signal from the specific state to a next state, are held. When the state monitoring circuit decides that the state of the state machine is the specific state, the state machine outputs a signal indicating the specific state as a state output of the state machine, and the BIST circuit performs a test of the state machine. When the transition request detection circuit detects the transition request signal while the test is performed, the BIST circuit stops the test of the state machine.

主权项

1. A semiconductor integrated circuit, comprising:
a state machine configured to generate a next state based on a current state and an external input, and to output a state signal indicating the current state; a test circuit configured to perform a test of the state machine in a test mode; a monitoring circuit configured to monitor, in a normal operation mode, whether or not a state of the state machine is a first state based on the state signal; and a detection circuit configured to detect, in the test mode, a transition request signal requesting a transition of the state of the state machine from the first state to a second state, wherein when the monitoring circuit decides that the state of the state machine is the first state in the normal operation mode, a mode transfers from the normal operation mode to the test mode, the test circuit performs the test of the state machine, and the state machine continues to output information indicating the first state by the state signal regardless of the state of the state machine in the test mode, and when the detection circuit detects the transition request signal in the test mode, the mode transfers from the test mode to the normal operation mode, the test circuit stops the test of the state machine.