发明名称 |
Optimizing error floor performance of finite-precision layered decoders of low-density parity-check (LDPC) codes |
摘要 |
Systems and methods are provided for selecting precisions during iterative decoding with a low-density parity check (LDPC) decoder in order to maximize LDPC code's performance in the error floor region. The selection of the precision of the messages may be done in such a way as to avoid catastrophic errors and to minimize the number of near-codeword errors during the decoding process. Another system and method to avoid catastrophic errors in the layered (serial) LDPC decoder is provided. Lastly, a system and method that select precisions and provide circuitry that optimizes the exchange of information between a soft-input, soft-output (SISO) channel detector and an error correction code (ECC) decoder for channels with memory is provided. |
申请公布号 |
US9256487(B1) |
申请公布日期 |
2016.02.09 |
申请号 |
US201414283718 |
申请日期 |
2014.05.21 |
申请人 |
Marvell International Ltd. |
发明人 |
Varnica Nedeljko;Burd Gregory;Gunnam Kiran |
分类号 |
H03M13/00;G06F11/07;H03M13/11 |
主分类号 |
H03M13/00 |
代理机构 |
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代理人 |
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主权项 |
1. A system comprising:
memory circuitry configured to store check node messages and variable node messages; and processing circuitry configured to:
update a variable node message of stored variable node messages; anddetermine if the variable node message is saturated based on a precision of the variable node message. |
地址 |
Hamilton BM |