Clock skew compensation with adaptive body biasing in three-dimensional (3D) integrated circuits (ICs) (3DICs)

摘要

Clock skew compensation with adaptive body biasing in three-dimensional (3D) integrated circuits (ICs) (3DICs) is disclosed. In one aspect, a sensor is placed on each tier of a 3DIC to evaluate a speed characteristic of each tier relative to the speed characteristic of another tier. Based on determining the relative speed characteristics, a control signal may be provided to adjust back body bias elements for clock buffers. Adjusting the back body bias effectively adjusts a threshold voltage of the clock buffers. Adjusting the threshold voltage of the clock buffers has the effect of slowing down or speeding up the clock buffers. For example, slow clock buffers may be sped up by providing a forward body bias and fast clock buffers may be slowed down by providing a reverse body bias. By speeding up slow elements and slowing down fast elements, compensation for the relative speed characteristics may be provided.

主权项

1. A three-dimensional (3D) integrated circuit (IC) (3DIC) comprising:
a first tier having a first speed characteristic, the first tier comprising:
one or more first clock buffers served by a first portion of a clock tree;a first sensor configured to detect the first speed characteristic for both n-type and p-type clock buffers in the first tier and generate a first output indicative of the first speed characteristic; anda first skew compensator configured to provide a first adjusted delay for at least one of the one or more first clock buffers based on the first output indicative of the first speed characteristic and not adjusting non-clock buffers in the first tier; and a second tier having a second speed characteristic, the second tier comprising:
one or more second clock buffers served by a second portion of the clock tree;a second sensor configured to detect the second speed characteristic for both n-type and p-type clock buffers in the second tier and generate a second output indicative of the second speed characteristic; anda second skew compensator configured to provide a second adjusted delay for at least one of the one or more second clock buffers based on the second output indicative of the second speed characteristic and not adjusting non-clock buffers in the second tier.