发明名称 記憶制御装置、記憶装置、および、それらにおける処理方法
摘要 A storage controlling apparatus includes a command decoder and command processing section. The command decoder decides whether or not a plurality of access object addresses of different commands included in a command string correspond to words different from each other in a same one of blocks of a memory cell array which have a common plate. The command processing section collectively and successively executes, when it is decided that the access object addresses of the commands correspond to the words different from each other in the same block of the memory cell array, those of operations in processing of the commands in which an equal voltage is applied as a drive voltage between the plate and a bit line.
申请公布号 JP5853843(B2) 申请公布日期 2016.02.09
申请号 JP20120099330 申请日期 2012.04.25
申请人 ソニー株式会社 发明人 藤波 靖;足立 直大;石井 健;大久保 英明;筒井 敬一;中西 健一;新橋 龍男
分类号 G11C13/00 主分类号 G11C13/00
代理机构 代理人
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