发明名称 Integrated circuit device, method for producing mask layout, and program for producing mask layout
摘要 According to one embodiment, a method for producing a mask layout of an exposure mask for forming wiring of an integrated circuit device, includes estimating shape of the wiring formed based on an edge of a pattern included in an initial layout of the exposure mask. The method includes modifying shape of the edge if the estimated shape of the wiring does not satisfy a requirement.
申请公布号 US9257367(B2) 申请公布日期 2016.02.09
申请号 US201313969823 申请日期 2013.08.19
申请人 Kabushiki Kaisha Toshiba 发明人 Okada Motohiro;Sota Shuhei;Hashimoto Takaki;Kai Yasunobu;Masukawa Kazuyuki;Kono Yuko;Kodama Chikaaki;Uno Taiga;Mashita Hiromitsu
分类号 G06F17/50;G06F19/00;G21K5/00;G03F1/00;H01L23/48;H01L23/528;G03F1/70 主分类号 G06F17/50
代理机构 Oblon, McClelland, Maier & Neustadt, L.L.P 代理人 Oblon, McClelland, Maier & Neustadt, L.L.P
主权项 1. A method for producing a mask layout of an exposure mask for forming wiring of an integrated circuit device, comprising: estimating, by a processor, shape of the wiring formed based on an edge of a pattern included in an initial layout of the exposure mask, wherein the shape of the wiring formed based on one of a plurality of edges of the pattern is estimated; and modifying, by a processor, shape of the edge if the estimated shape of the wiring does not satisfy a requirement, wherein the shape of the one edge is modified, the estimating and the modifying are repeated until the wiring with the estimated shape satisfies the requirement, the repeating is performed in order of arrangement of the edges for all the edges included in the initial layout; and further comprising producing the mask layout of the exposure mask based on the modified shapes of all of the edges after the repeating.
地址 Minato-ku JP