发明名称 集積回路、コンピュータシステム、制御方法
摘要 An integrated circuit provided with a processor includes a loop detection unit that detects execution of a loop in the processor, a loop-carried dependence analysis unit that analyzes the loop in order to detect loop-carried dependence, and a power control unit that performs power saving control when no loop-carried dependence is detected. By detecting whether a loop has loop-carried dependence, loops for calculation or the like can be excluded from power saving control. As a result, a larger variety of busy-waits can be detected, and the amount of power wasted by a busy-wait can be reduced.
申请公布号 JP5853216(B2) 申请公布日期 2016.02.09
申请号 JP20120521283 申请日期 2011.06.07
申请人 パナソニックIPマネジメント株式会社 发明人 杉山 真史;齊藤 雅彦
分类号 G06F1/32 主分类号 G06F1/32
代理机构 代理人
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