| 摘要 |
The present invention discloses a transient voltage suppression (TVS) device and a manufacturing method thereof. The TVS device limits a voltage drop between two terminals thereof not to exceed a clamp voltage. The TVS device is formed in a stack substrate including a semiconductor substrate, a P-type first epitaxial layer, and a second epitaxial layer stacked in sequence. In the TVS device, a first PN diode is connected to a Zener diode in series, wherein the series circuit is surrounded by a first shallow trench isolation (STI) region; and a second PN diode is connected in parallel to the series circuit, wherein the second PN diode is surrounded by a second STI region. The first STI region and the second STI region both extend from an upper surface to the second epitaxial layer, but not to the first epitaxial layer. |
| 主权项 |
1. A transient voltage suppression (TVS) device, which has a first terminal and a second terminal, for limiting a voltage drop between the first terminal and the second terminal not to exceed a clamp voltage, the TVS device comprising:
a semiconductor substrate, which has a P-type conductivity, and is used as or is electrically connected to the second terminal; a first epitaxial layer having the P-type conductivity, which is formed on and connected to the semiconductor substrate; a second epitaxial layer, which is formed on and connected to the first epitaxial layer, the second epitaxial layer having an upper surface; a cap layer having the P-type conductivity, which is formed in the first epitaxial layer, and is electrically connected to the second terminal; a first buried layer having an N-type conductivity, which is formed on the cap layer; a first N-type region having the N-type conductivity, which is formed in the second epitaxial layer on the first buried layer; a first P-type region having the P-type conductivity, which is formed in the second epitaxial layer on the first N-type region, and is electrically connected to the first terminal; a first shallow trench isolation (STI) region, which extends from the upper surface to the second epitaxial layer and connects the first buried layer, but the first STI region does not extend to the first epitaxial layer, and the first STI region surrounds the first N-type region and the first P-type region from a top view; a second P-type region having the P-type conductivity, which is formed in the first epitaxial or the second epitaxial layer on the semiconductor substrate, and is electrically connected to the second terminal; a second N-type region having the N-type conductivity, which is formed in the second epitaxial layer on and connected to the second P-type region, and is electrically connected to the first terminal; and a second STI region, which extends from the upper surface to the second epitaxial layer, but the second STI region does not extend to the first epitaxial layer, and the second STI region surrounds the second N-type region and the second P-type region from the top view; wherein a Zener diode includes the cap region and the first buried layer; a first PN diode includes the first P-type region and the first N-type region; a second PN diode includes the second P-type region and the second N-type region; wherein the first PN diode and the Zener diode are connected in series, the first N-type region being electrically connected to the first buried layer, and the second PN diode is connected in parallel to the series circuit of the first PN diode and the Zener diode, wherein the second PN diode and the series circuit of the first PN diode and the Zener diode are isolated by the first STI region and the second STI region in a lateral direction. |
