发明名称 プロセッサインストラクションの発行の絞り込み
摘要 A system and method for reducing power consumption through issue throttling of selected problematic instructions. A power throttle unit within a processor maintains instruction issue counts for associated instruction types. The instruction types may be a subset of supported instruction types executed by an execution core within the processor. The instruction types may be chosen based on high power consumption estimates for processing instructions of these types. The power throttle unit may determine a given instruction issue count exceeds a given threshold. In response, the power throttle unit may select given instruction types to limit a respective issue rate. The power throttle unit may choose an issue rate for each one of the selected given instruction types and limit an associated issue rate to a chosen issue rate. The selection of given instruction types and associated issue rate limits is programmable.
申请公布号 JP5853301(B2) 申请公布日期 2016.02.09
申请号 JP20120230295 申请日期 2012.09.28
申请人 アップル インコーポレイテッド 发明人 ダニエル シー マーレイ;アンドリュー ジェイ ボーモント−スミス;ジョン エイチ ミュリウス;ピーター ジェイ バノン;タカヤナギ トシ;ジュン ウク チョー
分类号 G06F15/78;G06F9/30;G06F9/38 主分类号 G06F15/78
代理机构 代理人
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