| 发明名称 | Platform power management for building wide control of power factor and harmonics | ||
| 摘要 | Example embodiments of an apparatus to reduce power consumed by a processor include a timing signal block configured to be coupled to measure the magnitude of an alternating current voltage signal supplied to a processor and to assert a timing signal when the magnitude of the alternating current voltage signal is about equal to zero volts and a throttling block configured to be coupled to the processor, to receive the timing signal and to assert a throttling signal that causes processor speed to be reduced so that processor power consumption is reduced in phase with the alternating current voltage signal and harmonic distortion of a current waveform supplied to the processor is reduced. | ||
| 申请公布号 | US9256270(B2) | 申请公布日期 | 2016.02.09 |
| 申请号 | US201113991747 | 申请日期 | 2011.12.29 |
| 申请人 | Intel Corporation | 发明人 | Rider Scott M. |
| 分类号 | G06F1/32;H02M1/42 | 主分类号 | G06F1/32 |
| 代理机构 | Buckley, Maschoff & Talwalkar LLC | 代理人 | Buckley, Maschoff & Talwalkar LLC |
| 主权项 | 1. An apparatus comprising: a timing signal block configured to be coupled to measure the magnitude of an alternating current voltage signal supplied to a processor and to assert a timing signal when the magnitude of the alternating current voltage signal is about equal to zero volts; and a throttling block configured to be coupled to the processor, to receive the timing signal and to assert a throttling signal that causes processor speed to be reduced so that processor power consumption is reduced in phase with the alternating current voltage signal and harmonic distortion of a current waveform supplied to the processor is reduced. | ||
| 地址 | Santa Clara CA US | ||