Data driving system and chip for liquid crystal panel as well as liquid crystal display device

摘要

A data driving system and a data driving chip for a liquid crystal panel as well as a liquid crystal display (LCD) device comprising the same are disclosed. The data driving system comprises a data driving chip, a timing controller and a first interface connected to the data driving chip and the timing controller. The first interface comprises a terminating resistor for converting a current signal transmitted through the first interface into a voltage signal, and the terminating resistor is disposed inside the data driving chip. By having the terminating resistor disposed inside the chip, the present disclosure can eliminate the need of additional electric tests, thus saving the cost of the additional electric tests.

主权项

1. A data driving chip for a liquid crystal panel, wherein the data driving chip is connected to the liquid crystal panel and a timing controller arranged on a control circuit board independent of the liquid crystal panel via a mini-LVDS (mini-Low Voltage Differential Signaling) interface embedded inside the data driving chip, the data driving chip with the mini-LVDS interface embedded therein is disposed on the liquid crystal panel, at least one X-circuit board is arranged between the timing controller arranged on the control circuit board and the data driving chip disposed on the liquid crystal panel for transmitting signals from the control circuit board to the data driving chip, the mini-LVDS interface comprises a terminating resistor embedded inside the mini-LVDS interface for converting a current signal transmitted through the mini-LVDS interface into a voltage signal, the terminating resistor is a programmable resistor whose resistance value can be adjusted according to setting codes,
wherein a storage chip is connected to the timing controller for storing the setting codes, and a pulse width modulation (PWM) chip is connected the timing controller, the data driving chip and the storage chip for supplying an operating voltage to the data driving chip, the timing controller and the storage chip respectively; wherein when a power input terminal is powered up, the PWM chip is activated to supply a first voltage and a second voltage to a logic portion and an analog portion respectively, then the time controller reads data from the storage chip into a register of the time controller, the setting codes for the resistance value of the terminating resistor are set in the mini-LVDS differential signal communication port of the data driving chip and the setting codes are transmitted to the data driving chip in one go before a RESET signal is activated, to accomplish one programming of this time, and the resistance value of the terminating resistor of the driving chip is kept constant until the setting codes disappear when the power is off.