| 摘要 |
PROBLEM TO BE SOLVED: To reduce jitter of the output clock of a PLL circuit.SOLUTION: A PLL circuit has a clock generation unit for generating an output clock having a frequency depending on a control voltage adjusted by a control signal, a frequency divider for receiving the output clock, and generating a frequency division clock by dividing the frequency of the output clock, a delay adjustment circuit for receiving the frequency division clock, and generating a feedback clock by adjusting the delay amount for the frequency division clock, and delaying the frequency division clock, and a phase comparator for receiving the input clock, output clock and feedback clock, detecting the phase difference between an output clock detected at a timing based on the feedback clock, and the input clock, and generating a control signal depending on the phase difference between the output clock and input clock.SELECTED DRAWING: Figure 1 |
