发明名称 NEGATIVE BIASED SUBSTRATE FOR PIXELS IN STACKED IMAGE SENSORS
摘要 A pixel cell includes a photodiode disposed within a first semiconductor chip for accumulating an image charge in response to light incident upon the photodiode. A transfer transistor is disposed within the first semiconductor chip and coupled to the photodiode to transfer the image charge from the photodiode. A bias voltage generation circuit disposed within a second semiconductor chip for generating a bias voltage. The bias voltage generation circuit is coupled to the first semiconductor chip to bias the photodiode with the bias voltage. The bias voltage is negative with respect to a ground voltage of the second semiconductor chip. A floating diffusion is disposed within the second semiconductor chip. The transfer transistor is coupled to transfer the image charge from the photodiode on the first semiconductor chip to the floating diffusion on the second semiconductor chip.
申请公布号 US2016037111(A1) 申请公布日期 2016.02.04
申请号 US201414448154 申请日期 2014.07.31
申请人 OMNIVISION TECHNOLOGIES, INC. 发明人 Dai Tiejun;Wang Rui;Tai Dyson H.;Manabe Sohei
分类号 H04N5/378;H01L27/146;H04N5/376 主分类号 H04N5/378
代理机构 代理人
主权项 1. A pixel cell, comprising: a photodiode disposed within a first semiconductor chip for accumulating an image charge in response to light incident upon the photodiode; a transfer transistor disposed within the first semiconductor chip and coupled to the photodiode to transfer the image charge from the photodiode; a bias voltage generation circuit disposed within a second semiconductor chip for generating a bias voltage, wherein the bias voltage generation circuit is coupled to the first semiconductor chip to bias the photodiode with the bias voltage, wherein the bias voltage is negative with respect to a ground voltage of the second semiconductor chip; and a floating diffusion disposed within the second semiconductor chip, wherein the transfer transistor is coupled to transfer the image charge from the photodiode on the first semiconductor chip to the floating diffusion on the second semiconductor chip.
地址 Santa Clara CA US