MEMORY MAPPING IN A PROCESSOR HAVING MULTIPLE PROGRAMMABLE UNITS

摘要

The disclosure includes, in general, among other aspects, an apparatus having multiple programmable units integrated within a processor. The apparatus has circuitry to map addresses in a single address space to resources within the multiple programmable units where the single address space includes addresses for different ones of the resources in different ones of the multiple programmable units and where there is a one-to-one correspondence between respective addresses in the single address space and resources within the multiple programmable units.

主权项

1. A processor comprising:
a synchronous dynamic random access memory (SDRAM) controller to couple to an SDRAM; a plurality of programmable multithreaded processors to process network packets, the plurality of programmable multithreaded processors having memory mapped registers; a reduced instruction set computer (RISC) processor coupled to the SDRAM controller and the plurality of programmable multithreaded processors, the RISC processor to receive and process packets from the plurality of programmable multithreaded processors; and circuitry to enable the RISC processor to transfer data between the memory mapped registers of the plurality of programmable multithreaded processors.