发明名称 |
INSTRUCTION AND LOGIC TO PROVIDE SIMD SECURE HASHING ROUND SLICE FUNCTIONALITY |
摘要 |
Instructions and logic provide SIMD secure hashing round slice functionality. Some embodiments include a processor comprising: a decode stage to decode an instruction for a SIMD secure hashing algorithm round slice, the instruction specifying a source data operand set, a message-plus-constant operand set, a round-slice portion of the secure hashing algorithm round, and a rotator set portion of rotate settings. Processor execution units, are responsive to the decoded instruction, to perform a secure hashing round-slice set of round iterations upon the source data operand set, applying the message-plus-constant operand set and the rotator set, and store a result of the instruction in a SIMD destination register. One embodiment of the instruction specifies a hash round type as one of four MD5 round types. Other embodiments may specify a hash round type by an immediate operand as one of three SHA-1 round types or as a SHA-2 round type. |
申请公布号 |
US2016034282(A1) |
申请公布日期 |
2016.02.04 |
申请号 |
US201514880166 |
申请日期 |
2015.10.09 |
申请人 |
Intel Corporation |
发明人 |
Wolrich Gilbert M.;Gopal Vinodh;Yap Kirk S. |
分类号 |
G06F9/38;G06F9/30;G06F15/80 |
主分类号 |
G06F9/38 |
代理机构 |
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代理人 |
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主权项 |
1. A processor comprising:
a plurality of SIMD registers; a decode stage to decode a first instruction for a SIMD (Single Instruction Multiple Data) secure hashing algorithm round slice, the first instruction specifying a source data operand set, a message-plus-constant operand set, a round-slice portion of the secure hashing algorithm round, and a rotator set portion of rotate settings; and one or more execution units, responsive to the decoded first instruction, to:
perform a secure hashing round-slice set of round iterations upon the source data operand set, applying the message-plus-constant operand set and the rotator set portion of rotate settings; andstore a result of the first instruction in a SIMD destination register. |
地址 |
Santa Clara CA US |