METHODS OF FORMING LOW RESISTANCE CONTACTS

摘要

Methods for forming electrical contacts are provided. First and second FETs are formed over a semiconductor substrate. Openings are etched in a dielectric layer formed over the substrate, where the openings extend to source and drain regions of the FETs. A hard mask is formed over the source and drain regions of FETs. A first portion of the hard mask is removed, where the first portion is formed over the source and drain regions of the first FET. First silicide layers are formed over the source and drain regions of the first FET. A second portion of the hard mask is removed, where the second portion is formed over the source and drain regions of the second FET. Second silicide layers are formed over the source and drain regions of the second FET. A metal layer is deposited within the openings to fill the openings.

主权项

1. A method for forming electrical contacts, the method comprising:
forming first and second field effect transistors (FETs) over a semiconductor substrate; forming a dielectric layer over the semiconductor substrate; etching openings in the dielectric layer that extend to i) source and drain regions of the first FET, and ii) source and drain regions of the second FET; forming a hard mask over the source and drain regions of the first and second FETs; removing a first portion of the hard mask, wherein the first portion is formed over the source and drain regions of the first FET; forming first silicide layers over the source and drain regions of the first FET by depositing a first metal layer over the source and drain regions of the first FET, and annealing the first metal layer to cause the first metal layer to react and form the first silicide layers; removing a second portion of the hard mask, wherein the second portion is formed over the source and drain regions of the second FET; forming second silicide layers over the source and drain regions of the second FET, wherein the second silicide layers are formed by depositing a second metal layer over the source and drain regions of the second FET, and annealing the second metal layer to cause the second metal layer to react and form the second silicide layers; and depositing a third metal layer within the openings to fill the openings.