Systems and methods for trimming control transistors for 3D NAND flash

摘要

Control transistors and memory cells within 3D NAND Flash memory arrays may both be created using the same technology, such as charge trapping structures, to simplify the fabrication process. However, the resulting control transistors may initially have higher variability in threshold voltages, when compared to traditional gate-oxide-based control transistors. Provided are exemplary techniques to trim control transistors to provide increased reliability and performance during array operation.

主权项

1. A system for controlling a memory array comprising a first string of memory cells and a second string of memory cells, the system comprising:
a group of control transistors for controlling the first and second strings of memory cells, the group of control transistors comprising:
a first string select transistor, a first upper ground select transistor, and a first ground select transistor, each operably connected to the first string of memory cells; anda second string select transistor, a second upper ground select transistor, and a second ground select transistor, each operably connected to the second string of memory cells,wherein the first string select transistor is operable to connect the first string of memory cells to a bit line; andwherein the second string select transistor is operable to connect the second string of memory cells to the bit line; and a controller operable to trim the first and second string select transistors, the first and second upper ground select transistors, and the first and second ground select transistors, thereby changing the threshold voltages of the control transistors that are trimmed, wherein the controller is further operable to inhibit programming of the second upper ground select transistor during a time when the first upper ground select transistor is trimmed.