SYSTEM AND METHOD FOR CLOCK GENERATION WITH AN OUTPUT FRACTIONAL FREQUENCY DIVIDER

摘要

A system and a method generate clock signals using an output divider with modulus steps of half-integers (i.e., the output circuit includes a divider which divides by one or more of 2, 2.5, 3, 3.5, 4 . . . ).

主权项

1. A clock signal generation circuit, comprising:
a phase-locked loop including a voltage-controlled oscillator, receiving an input clock signal and providing an output signal phase-locked to the input clock signal; and a frequency divider circuit providing a plurality of output signals of various frequencies, wherein the various frequencies include both an integer submultiple and a half-integer submultiple of the frequency of the output signal of the phase-locked loop.