| 发明名称 |
TRAP RICH LAYER FOR SEMICONDUCTOR DEVICES |
| 摘要 |
An integrated circuit chip is formed with an active layer and a trap rich layer. The active layer is formed with an active device layer and a metal interconnect layer. The trap rich layer is formed above the active layer. In some embodiments, the active layer is included in a semiconductor wafer, and the trap rich layer is included in a handle wafer. |
| 申请公布号 |
US2016035833(A1) |
申请公布日期 |
2016.02.04 |
| 申请号 |
US201514855652 |
申请日期 |
2015.09.16 |
| 申请人 |
Silanna Semiconductor U.S.A., Inc. |
发明人 |
Brindle Christopher N.;Stuber Michael A.;Molin Stuart B. |
| 分类号 |
H01L29/10;H01L27/12;H01L23/00;H01L25/065;H01L23/528;H01L21/84;H01L25/00 |
主分类号 |
H01L29/10 |
| 代理机构 |
|
代理人 |
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| 主权项 |
|
| 地址 |
San Diego CA US |
