UNCORRECTABLE MEMORY ERRORS IN PIPELINED CPUS

摘要

Uncorrectable memory errors in pipelined central processing units. A processor core may be connected to a memory system and it may include a processor cache. In response to determining an uncorrectable error in data stored in the memory system, the address of a memory location of the uncorrectable error is stored in an address buffer and a recovery procedure is performed for the processor core. When fetching data from a memory location and if it is determined that the address of this memory location is stored in the address buffer, the content of a cache line related to the address is moved into a quarantine buffer of the processor core. When detecting an error in the data of the moved cache line, a repair procedure for the data of this address is triggered.

主权项

1. A method of performing error recovery by a processor core connected to a main memory system and comprising a processor cache, the method comprising:
based on determining an uncorrectable error in data stored in the main memory system, storing an address of a memory location of the uncorrectable error in an address buffer and performing a recovery procedure for the data; based on fetching data from a selected memory location and determining that the address of the selected memory location is stored in the address buffer, moving content of a cache line related to the address into a quarantine buffer of the processor core; and based on detecting an error in the data of the moved cache line, triggering a repair procedure for data of the address.