发明名称 LEVEL SHIFT CIRCUIT, ELECTRO-OPTICAL APPARATUS, AND ELECTRONIC EQUIPMENT
摘要 To realize a level shift circuit with the small occupation area and capable of performing high-speed operation, a level shift circuit includes an electric potential converting unit that converts a first electric potential of an input signal to a third electric potential and converts a second electric potential of an input signal to a fourth electric potential. A capacitor includes first and second electrodes, the first electrode being electrically connected to the input unit, and the second electrode being electrically connected to an output node of the electric potential converting unit. A buffer unit converts the third and fourth electrical potentials to fifth and sixth electrical potentials, respectively. The capacitor reflects the input signal in the electric potential of the output node of the electric potential converting unit without delay by capacitive coupling, thereby realizing a level shift circuit that is capable of performing high-speed operation.
申请公布号 US2016035295(A1) 申请公布日期 2016.02.04
申请号 US201414775681 申请日期 2014.03.11
申请人 SEIKO EPSON CORPORATION 发明人 FUJIKAWA Shinsuke
分类号 G09G3/36 主分类号 G09G3/36
代理机构 代理人
主权项 1. A level shift circuit comprising: an electric potential converting unit that is electrically connected between a first node and a second node, converts a first electric potential to a third electric potential, and converts a second electric potential to a fourth electric potential; a buffer unit that is electrically connected to the second node, converts the third electric potential to a fifth electric potential, and converts the fourth electric potential to a sixth electric potential; and a capacitor that is electrically connected between the first node and the second node, wherein the electric potential converting unit includes a first transistor in which a source and a drain are electrically connected between the first node and the second node, and a gate is electrically connected to the second node,a second transistor in which a source or a drain is electrically connected to the second node, and a gate is electrically connected to the second node, and wherein the capacitor includesa third transistor in which a gate is electrically connected to the first node and a source and a drain are electrically connected to the second node.
地址 Shinjuku-ku, Tokyo JP