DUAL MODE TEST ACCESS PORT METHOD AND APPARATUS

摘要

An integrated circuit has controller circuitry having coupled to a test clock and a test mode select inputs, and having state a register clock state output, a register capture state output, and a register update state output. Register circuitry has a test data in lead input, control inputs coupled to the state outputs of the controller circuitry, and a control output. Connection circuitry has a control input connected to the control output of the register circuitry and selectively couples one of a first serial data output of first scan circuitry and a second serial data output of second scan circuitry to a test data out lead. Selection circuitry has an input connected to the serial data input lead, an input connected to a test pattern source lead, a control input coupled to the scan circuitry control output leads, and an output connected to the scan input lead.

主权项

1. An integrated circuit comprising:
(A) a test data in lead, a test data out lead, a test clock lead, and a test mode select lead; (B) test access port circuitry including an instruction register having an input coupled to the test data in lead and an output, and a data register having an input coupled to the test data in lead and an output; (C) multiplexer circuitry having one input coupled to the output of the instruction register, another input coupled to the output of the data register, and an output coupled to the test data out lead; (D) a bypass register, separate from the test access port circuitry, having an input coupled to the test data in lead and an output; and (E) gating circuitry, separate from the multiplexer circuitry, selectively coupling the output of the bypass register to the test data out lead.