SORTING DECODER

摘要

A sorting decoder captures the rank-order of a set of input analogue signals in the digital domain using simple logic components such as self-timed first state elements, without requiring conventional analogue-to-digital signal converters. The analogue signals are each compared against a monotonic dynamic reference and the resulting comparisons are snapshot by a self-timed first state element for each input signal, or the last member of a sorted collection of input signals, at the time when it reaches the reference signal, so that a different snapshot representing the signal value ranking relative to the other signal values is produced for each input signal. The resulting rank-order estimation snapshots are binary signals that can then be further processed by a simple sorting logic circuit based on elementary logic components.

主权项

1. A sorting decoder comprising:
a dynamic reference generator configured to generate a monotonic dynamic reference signal; a set of n comparators, each comparator configured to operate on (i) a respective input signal of a set of n input signals and (ii) the monotonic dynamic reference signal, the set of n comparators configured to form a set of n comparator outputs; a first logic circuit configured to detect when N comparator outputs of the set of n comparator outputs have a low state and n-N remaining comparator outputs have a high state and output a first latching signal, the N comparator outputs corresponding to a set of N most positive input signals, wherein 1≦N