发明名称 STACK PACKAGES AND METHODS OF MANUFACTURING THE SAME
摘要 A stack package includes a substrate having connection terminals and a first chip on the substrate. The first chip has first connectors on edges thereof. A second chip is stacked on the first chip to expose outer portions of the first connectors. The second chip has second connectors on edges thereof. Connection members to connect the exposed outer portions of the first connectors to the connection terminals. Sidewall interconnectors to connect the exposed outer portions of the first connectors to the second connectors. The sidewall interconnectors extend from the exposed outer portions of the first connectors along sidewalls of the second chip to cover the second connectors.
申请公布号 US2016035708(A1) 申请公布日期 2016.02.04
申请号 US201514884864 申请日期 2015.10.16
申请人 SK hynix Inc. 发明人 BAE Jin Ho;BAE Han Jun
分类号 H01L25/065;H01L23/00 主分类号 H01L25/065
代理机构 代理人
主权项 1. A stack package comprising: a substrate having bond fingers; a first chip on the substrate, the first chip having first connectors on edges thereof; a second chip stacked on the first chip to expose outer portions of the first connectors, the second chip having second connectors on edges thereof; a third chip stacked on the second chip to expose outer portions of the second connectors, the third chip having third connectors on edges thereof; metal wires to electrically connect the exposed outer portions of the first connectors to the bond fingers; and sidewall interconnectors to electrically connect the exposed outer portions of the first connectors to the second connectors and the third connectors wherein a portion of the sidewall interconnectors surround a first end portion of the metal wires.
地址 Icheon-si Gyeonggi-do KR