| 发明名称 |
BACKSIDE THROUGH SILICON VIAS AND MICRO-CHANNELS IN THREE DIMENSIONAL INTEGRATION |
| 摘要 |
Technologies are generally described related to electrical connectivity and heat mitigation in three dimensional integrated circuit (IC) integration through backside through silicon vias (TSVs) and micro-channels. In some examples, micro-channels may be formed in a wafer using a reactive ion etching (RIE) or similar fabrication process. Upon alignment and bonding of two wafers, selected micro-channels may be converted into TSVs by a further RIE or similar process and filled. |
| 申请公布号 |
US2016035704(A1) |
申请公布日期 |
2016.02.04 |
| 申请号 |
US201414450203 |
申请日期 |
2014.08.01 |
| 申请人 |
Empire Technology Development LLC |
发明人 |
Luo Zhijiong |
| 分类号 |
H01L25/065;H01L23/48;H01L21/67;H01L21/768;H01L21/3065;H01L21/285;H01L25/00;H01L23/532 |
主分类号 |
H01L25/065 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A three-dimensionally integrated semiconductor device comprising:
a first wafer including a plurality of micro-channels within a substrate of the first wafer and one or more through silicon vias (TSVs) within the substrate and an insulating layer of the first wafer; and a second wafer, wherein the one or more TSVs are configured to contact the second wafer and at least a portion of the one or more TSVs is configured to overlap with corresponding micro-channels. |
| 地址 |
Wilmington DE US |
