WAVEFORM EQUALIZATION APPARATUS

摘要

A waveform equalization apparatus includes an A/D converter, a waveform equalizer, a training sequence generator, a clock recovery circuit, multiple matched filters, and a clock optimization logic. The A/D converter oversamples a reception signal in synchronization with a base clock signal and generates an A/D converted data sequence. The waveform equalizer performs an arithmetic operation to equalize a waveform. The training sequence generator generates a data sequence for training. The data sequence for training is used instead of an output data of the detector so as to converge a coefficient used in the arithmetic operation in advance. The clock recovery circuit supplies the base clock signal without executing a clock recovery operation during a training period, and executes the clock recovery operation according to the output data of the detector. The matched filters receive the A/D converted data sequence, and execute a filter arithmetic operation.

主权项

1. A waveform equalization apparatus comprising:
an analog-to-digital (A/D) converter oversampling a reception signal in synchronization with a base clock signal to generate an A/D converted data sequence; a waveform equalizer performing an arithmetic operation to equalize a waveform regarding the A/D converted data sequence in synchronization with the base clock signal, wherein the waveform equalizer includes a detector at an output stage; a training sequence generator generating a data sequence for training, wherein the data sequence for training is used so as to converge a coefficient used in the arithmetic operation in advance, the data sequence for training is used instead of an output data of the detector, wherein the training sequence generator is used during a training period; a clock recovery circuit
supplying the base clock signal without executing a clock recovery operation during the training period, andafter termination of the training period, executing the clock recovery operation according to the output data of the detector and generating and outputting the base clock signal; a plurality of matched filters
receiving the A/D converted data sequence, andexecuting a filter arithmetic operation to correlate the data sequence for training with the A/D converted data sequence in synchronization with a multiphase clock signal having a frequency that corresponds to speed of the reception signal; and a clock optimization logic supplying the training sequence generator with a predetermined optimum operation clock signal based on the multiphase clock signal and output data of the plurality of the matched filters.