GENERATING A HASH USING S-BOX NONLINEARIZING OF A REMAINDER INPUT

摘要

A processor includes a hash register and a hash generating circuit. The hash generating circuit includes a novel programmable nonlinearizing function circuit as well as a modulo-2 multiplier, a first modulo-2 summer, a modulor-2 divider, and a second modulo-2 summer. The nonlinearizing function circuit receives a hash value from the hash register and performs a programmable nonlinearizing function, thereby generating a modified version of the hash value. In one example, the nonlinearizing function circuit includes a plurality of separately enableable S-box circuits. The multiplier multiplies the input data by a programmable multiplier value, thereby generating a product value. The first summer sums a first portion of the product value with the modified hash value. The divider divides the resulting sum by a fixed divisor value, thereby generating a remainder value. The second summer sums the remainder value and the second portion of the input data, thereby generating a hash result.

主权项

1. A method comprising:
(a) storing an amount of incoming data in a processor, wherein the amount of incoming data comprises a first portion and a second portion; (b) maintaining a hash register value in a hash register; (c) supplying the first portion of the amount of incoming data onto a set of input leads of a modulo-2 multiplier; (d) using the modulo-2 multiplier to modulo-2 multiply the first portion by a multiplier value thereby generating a product value, wherein the product value comprises a first portion and a second portion; (e) using a programmable nonlinearizing function circuit to perform a nonlinearizing function on the hash register value and thereby generating a modified version of the hash register value; (f) using a first modulo-2 summer to modulo-2 sum the first portion of the product value and the modified version of the hash register value and thereby generating a first sum value; (g) using a modulo-2 divider to modulo-2 divide the first sum value by a divisor value and thereby outputting a division remainder value; (h) using a second modulo-2 summer to modulo-2 sum the second portion of the product value and the division remainder value; and (i) loading the division remainder value into the hash register, wherein (a) through (i) are performed by the processor, and wherein the hash register, the modulo-2 multiplier, the programmable nonlinearizing function circuit, the first modulo-2 summer, the modulo-2 divider, and the second modulo-2 summer are parts of the processor.