| 摘要 |
<p>A CMOS receiver operates from the same voltage DVDD (which may be 1.8 V, 2.5 V or 3.3 V) as the circuit from which input signals are received at node 50, the various gate tracking circuits PGT and NGT allowing the use of 1.8 V transistors throughout. The intermediate node voltages at the gates of the transistors 235 and 230 follow the input signal respectively in higher and lower sub-ranges of the input signal voltage range, but are clamped outside these sub-ranges (figure 6) to protect the devices 235 and 230 from overvoltage. The REFP reference voltage is set equal to DVDD minus a fixed voltage. A good noise margin between logic level threshold voltages VIH and VIL levels may be obtained at all values of DVDD. The noise margin may be further improved by enabling the hysteresis circuits 300 and 315. The pull-up of nodes A and D0, which is achieved by device 265 in response to the fall of node 245, may be accelerated by circuit 285 which responds to the fall of node 250.</p> |
