发明名称 MEMS表示デバイス用のラッチ回路
摘要 The described latching circuits can be formed using transistors of a single conductivity type. The transistors can be n-type transistors or p-type transistors. The latching circuits include at least one pre-charge transistor and at least one output terminal discharge transistor. Timing schemes are also described for operating the latching circuits. Pixel circuits and display devices that include these latching circuits are also described. The display devices are formed from an arrangement of the latching circuits.
申请公布号 JP5851594(B2) 申请公布日期 2016.02.03
申请号 JP20140513703 申请日期 2012.05.31
申请人 ピクストロニクス,インコーポレイテッド 发明人 宮沢 敏夫;宮本 光秀
分类号 G09G3/34;G02B26/02;G09G3/20 主分类号 G09G3/34
代理机构 代理人
主权项
地址