发明名称 半導体集積回路装置及びそれを用いたシステム
摘要 The present invention provides a semiconductor integrated circuit device realizing improved detection of a failure while suppressing deterioration in performance. In a semiconductor integrated circuit device executing a plurality of threads while switching them synchronously with clocks, registers used for executing the threads are provided for the respective threads. Programs independent of each other and the same program as the threads are executed while being switched. In the case of executing the same program by a plurality of threads, a comparison circuit for comparing results of execution using registers provided in correspondence with the threads is provided.
申请公布号 JP5850774(B2) 申请公布日期 2016.02.03
申请号 JP20120064785 申请日期 2012.03.22
申请人 ルネサスエレクトロニクス株式会社 发明人 山田 弘道;金川 信康;山田 勉;萩原 今朝巳
分类号 G06F11/18;G06F9/46 主分类号 G06F11/18
代理机构 代理人
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