发明名称 Allocation of tiles to processing engines in a graphics processing system
摘要 Primitive fragments are processed in a graphics processing system using a rendering space sub-divided into tiles. Texturing and/or shading is applied to the fragments by processing engines (216) in the system. A cache (218) (e.g. a multi-level cache) in the system stores graphics data for the fragments, the cache including multiple cache subsystems (220). Each subsystem is coupled to a respective set of one or more processing engines. A tile allocation unit (224) in the system operates in one or more allocation modes to allocate tiles to the processing engines. The allocation mode(s) include a spatial allocation mode in which groups of spatially adjacent tiles (e.g. 2x2 groups) are allocated to the processing engines according to a spatial allocation scheme, which ensures that each group of spatially adjacent tiles is allocated to a set of processing engines coupled to the same cache subsystem. Fragments in spatially adjacent tiles thereby get sent to processing engines coupled to the same cache subsystem, improving cache efficiency. One or more of the allocation modes may include a load balancing allocation mode in which tiles are allocated to engines based on computational loads of the engines.
申请公布号 GB201522540(D0) 申请公布日期 2016.02.03
申请号 GB20150022540 申请日期 2015.12.21
申请人 IMAGINATION TECHNOLOGIES LTD. 发明人
分类号 主分类号
代理机构 代理人
主权项
地址