| 摘要 |
The present invention relates to bit interleaving and de-interleaving of quasi-cyclic low-density parity-check (QC-LDPC) codes and discloses a bit interleaver that allows for a particularly efficient hardware implementation due to its high degree of parallelism. This is achieved by constructing a permutation for mapping the bits of the QC-LDPC codeword to a sequence of constellation words such that the permutation can be performed independently for each of N/M sections of the codeword, wherein N is the number of cyclic blocks within the codeword and M the number of bits per constellation word. According to a further aspect of the present invention, each section permutation may be further sub-divided into a plurality of intra-cyclic group permutations performed independently on the Q bits of each cyclic group, followed by a column-row permutation of the M · Q bits of the entire section. |
