| 摘要 |
953,890. Circuits employing bi-stable magnetic elements. SIEMENS & HALSKE A.G. Nov. 30, 1960 [Nov. 30, 1959; Dec. 1, 1959; March 30, 1960], No. 41199/60. Heading H3B. [Also in Division G4] A register or series-to-parallel converter comprises a series of transfluxors having three or four apertures. Basic three-aperture transfluxor. The apertured core is provided with input and output windings E, A, Fig. 2a, a transfer winding U and a clearing winding B. The magnetic condition shown in Fig. 2b is produced when the clearing winding is energized by a clock pulse. A binary signal represented by the presence or absence of a pulse is next applied to the input winding, a binary one input causing the flux condition to be modified as shown in Fig. 2c. The transfer winding is then energized by a clock pulse. If a zero is stored, Fig. 2b, this pulse is without effect, but if a binary one is stored, Fig. 2c, the direction of the flux about the right-hand aperture is transferred or reversed, as shown in Fig. 2d. A further input pulse which may occur after this time cannot establish the flux condition resulting from the transfer operation. When an output is required from the transfluxor, a clearing pulse is applied to winding B which restores the flux to the state shown in Fig. 2b in readiness for storage of the next digit. Register controlled by a clock pulse distributer. In Fig. 1, transfluxors TR1, TR2, TR3, each with three apertures, are cyclically pulsed in turn by a clock pulse distributer TV. The first serial input pulse is applied to commoned input windings E1, E2, E3 in the period between clock pulses I 1 and I 2 which are respectively applied to the clear and transfer windings, and a registration is effected in transfluxor TR1. Similarly the second serial digit is applied between" clock pulses I 3 and I 4 for registration in TR2 and so on. Duplicate registration on a preceding transfluxor in the series cannot take place as the transfer operation has been effected on that core. Read-out is effected serially in commoned output windings A1, A2, A3 during the second clock pulse cycle as each transfluxor is cleared in turn. In a modification, Fig. 4, adjacent clear and transfer windings U and B are serially connected to the pulse distributer so that one transfluxor is brought to the transfer state at the same time as the next in the series is cleared. Series-to-parallel converter controlled by a pulse distributer. The distributer circuit of Fig. 4 is used in Fig. 5 in which the serial input Ie is applied simultaneously to all the transfluxors. When registration is complete, the transfluxors are simultaneously cleared by a pulse Il applied to commoned erase windings L1, L2, L3, and parallel outputs are thereby produced in output windings A1, A2 and A3. Basic transfluxor with four apertures. The input winding E in this arrangement is linked with the fourth apertures, Fig. 6a, and additional windings comprise an auxiliary input winding V, clock winding Ta and control winding S. In addition the clearing winding comprises two sections B1 and B2. As previously described, a binary one registration sets up the flux condition shown in Fig. 2c, which is modified as shown in Fig. 2d when the transfer winding is pulsed. In the present arrangement both of these flux conditions are modified about the left-hand aperture as shown in Fig. 6b when the auxiliary input winding V is pulsed. The magnetization about this aperture is restored when a clock pulse It is applied to winding Ta. This restoration has the effect of inducing a pulse in the control winding S and so causing a transistor T to conduct. Clearing of the core then commences, and is continued by feed-back between windings B1 and B2 which maintains the transistor conductive until clearing is complete. Register using four-apertured transfluxors. Each transistor T1, T2, T3, Fig. 7, has its emitter-collector circuit included in series with the auxiliary input winding on the next transfluxor stage, and when a start signal is applied to the auxiliary input winding V1 on the first stage Tr1, a clearing operation is initiated in this stage in response to a clock pulse It which continues through the stage as further clock pulses are received. As each transfluxor is cleared, it causes a transfer operation in the stage immediately preceding. Registration and readout of a serial input signal takes place as in Figs. 1, 4 and 5. A modification is described, Fig. 8, in which the clear output from one transfluxor sets a storage core M provided between adjacent transistors T1, T11. This core is reset by a clock pulse It, and applies a pulse over transistor T11, to the auxiliary input winding on one stage and the transfer winding on the stage immediately preceding. In place of a single output winding A, each transfluxor may have two output windings A1, All, interconnected as shown in Fig. 10 for serial output and Fig. 11 for parallel output, so that when the associated transfluxor is cleared a pulse appears in one winding if a binary zero is stored and in the other winding when storing a binary one. Transfluxors with three apertures controlled by transfluxors with four apertures. As shown in Fig. 9, columns of transfluxors Tr1, Tr11 and Tr2, Tr12 are respectively controlled by transfluxors Tr21, Tr22, independent input signals Ie1, Ie2 and Ie3 being applied to each row. Stepwise operation of the four-apertured transfluxors Tr21, Tr22 is effected under the control of clock pulse It as described previously. Three-apertured transfluxors operating without a pulse distributer as parallel-series converters. In Fig. 12 the transfluxors Tr1, Tr2, Tr3 are provided with auxiliary input windings, clock windings and control windings, and divided clearing windings associated with transistors are used as in the four aperture embodiments. The input windings in this embodiment are, however, arranged through the same apertures as the output windings so that simultaneous inputs Ie1, Ie2, Ie3 establish a characterizing flux condition which is removed as the transfluxors become sequentially cleared by the clock pulse. An alternative converter is shown in Fig. 13 which provides pulses representing stored binary one values in one winding group A1 and pulses representing binary zero in another winding group A2. In operation the transfluxors are simultaneously cleared by a pulse Iev. The input signals are then applied to windings E. Sequential transfer of the cores then takes place when transfer winding U is pulsed by Is. This pulse is followed by a clock pulse It which causes control and feed-back windings S and R to apply a signal over a transistor T1 to the transfer winding on the next transfluxor, and so on. In this arrangement the outputs are produced by the transfer operation. Parallel-to-series converter controlled by a clock pulse distributer. As shown in Fig. 14, the transfluxors are initially cleared by windings B1-B3, and the input pulses are applied simultaneously to respective input windings E1-E3. Outputs are induced serially in windings A1, A2 and A3 as the respective transfluxors have their transfer windings U1, U2, U3 energized sequentially from a pulse distributer TV. |
