Impedance matching between FPGA and memory modules

摘要

Embodiments of the present invention provide impedance matching between a Field Programmable Gate Array (FPGA) and memory modules in a semiconductor storage device (SSD) system architecture. Specifically, a set (at least one) of memory modules is coupled to an FPGA. A damping resistor is placed at the impedance mismatching point to reduce signal noise.

主权项

1. A data storage device in a semiconductor storage device (SSD) system architecture, comprising:
a controller board coupled to a set of memory modules by a transmission channel configured to communicate data using a digital transmission standard; and a damping resistor connecting in a three-way manner with the controller board, the set of memory modules, and a voltage source that is externally connected to the controller board; wherein each memory module of the set of memory modules and the voltage source are disposed on one side of the damping resistor along the transmission channel and the controller board is disposed on the other side of the damping resistor along the transmission channel; and wherein the controller board comprises a programmable integrated circuit and the damping resistor is configured to match configurable impedance of the programmable integrated circuit of the controller board with both impedance of the whole set of memory modules and impedance of the voltage source, such that signal noise at the three-way connection is reduced.