Pixel of a multi-stacked CMOS image sensor and method of manufacturing the same

摘要

Provided is a pixel of a multi-stacked complementary metal-oxide semiconductor (CMOS) image sensor and a method of manufacturing the image sensor including a light-receiving unit that may include first through third photodiode layers that are sequentially stacked, an integrated circuit (IC) that is formed below the light-receiving unit, electrode layers that are formed on and below each of the first through third photodiode layers, and a contact plug that connects the electrode layer formed below each of the first through third photodiode layers with a transistor of the IC.

主权项

1. A pixel of a multi-stacked complementary metal-oxide semiconductor (CMOS) image sensor, the pixel comprising:
a light-receiving unit comprising: a first subpixel unit, a second subpixel unit located above the first subpixel unit, and a third subpixel unit located above the second subpixel unit, wherein the light receiving unit is substantially rectangular in shape and has a first side and has an adjacent second side; an integrated circuit (IC) located in the bottom of the pixel, and at least partially located below the light receiving unit; a first extension electrode unit extending from the first subpixel and extending out of the first side of the light receiving unit; a second extension electrode unit extending from the second subpixel and extending out of the first side of the light receiving unit; a third extension electrode unit extending from the third subpixel unit and extending out of the first side of the light receiving unit; a fourth extension electrode unit extending out of the adjacent second side of the light receiving unit, wherein the fourth extension electrode unit extends orthogonally with respect to the first extension electrode unit; a first contact plug connecting the first extension electrode unit to a first transistor in the IC; a second contact plug connecting the second extension electrode to a second transistor in the IC; a third contact plug connecting the third extension electrode to a third transistor in the IC; and a fourth contact plug connecting the fourth extension electrode to a common electrode terminal, wherein the first, second, and third extension electrode units are laterally offset in a plan view.