发明名称 Chip package
摘要 A chip of a chip package comprises a substrate having a chip circuit, a chip selection terminal connecting to the chip circuit, multiple first conductors separated at different levels by multiple insulation layers, multiple first vertical connections respectively connecting to the first conductors and extending to a substrate surface, multiple second vertical connections respectively connecting to the first conductors and extending to a surface of the insulation layers, a third vertical connection electrically connecting to the chip selection terminal and extending to the substrate surface, a fourth vertical connection formed through the insulation layers and the substrate, a second conductor formed on the surface of the insulation layers and connecting to the fourth vertical connection, multiple first pads respectively connecting to the first vertical connections and the third vertical connection, and multiple second pads respectively connecting to the second vertical connections.
申请公布号 US9252105(B2) 申请公布日期 2016.02.02
申请号 US201414155590 申请日期 2014.01.15
申请人 NANYA TECHNOLOGY CORPORATION 发明人 Lin Po Chun
分类号 H01L29/40;H01L23/538;H01L25/07;H01L23/522 主分类号 H01L29/40
代理机构 WPAT, P.C. 代理人 WPAT, P.C. ;King Anothony
主权项 1. A chip package comprising at least one chip, the at least one chip comprising: a substrate; a chip circuit formed on the substrate; a plurality of insulation layers formed on the substrate; a chip selection terminal formed on the substrate or within the insulation layers and connecting to the chip circuit for enabling the chip circuit; a plurality of first conductors separated at different levels by the plurality of insulation layers; a plurality of first vertical connections respectively connecting to the plurality of first conductors and extending to a surface of the substrate opposite to the plurality of insulation layers; a plurality of second vertical connections respectively connecting to the plurality of first conductors and extending to a surface of the plurality of insulation layers opposite to the substrate; a third vertical connection electrically connecting to the chip selection terminal and extending to the surface of the substrate; a fourth vertical connection formed through the plurality of insulation layers and the substrate; a second conductor formed on the surface of the plurality of insulation layers and connecting to the fourth vertical connection; a plurality of first pads formed on the surface of the substrate and respectively connecting to the plurality of first vertical connections, the third vertical connection and the fourth vertical connection; and a plurality of second pads formed on the surface of the plurality of insulation layers and respectively connecting to the plurality of second vertical connections.
地址 Taoyuan TW