发明名称 Enhanced performance monitoring method and apparatus
摘要 A high-performance-computer system includes a statistics accumulation apparatus configured to efficiently accumulate system performance data from a variety of system components, and periodically write such data to processor local memory for efficient subsequent software processing of the thus acquired data, thereby reducing the system hardware and software overhead needed for collection of such data as compared to prior art systems.
申请公布号 US9250826(B2) 申请公布日期 2016.02.02
申请号 US201313801841 申请日期 2013.03.13
申请人 Silicon Graphics International Corp. 发明人 Fromm Eric Carl
分类号 G06F13/00;G06F3/06;G06F11/30;G06F11/34 主分类号 G06F13/00
代理机构 Sunstein Kann Murphy & Timbers LLP 代理人 Sunstein Kann Murphy & Timbers LLP
主权项 1. A computer processing system having a processer and a local memory logically coupled to the processor, the computer processing system comprising: a plurality of performance monitoring components distributed throughout the computer processing system; a statistics accumulation apparatus comprising: a plurality of prescalers, each of the plurality of prescalers logically coupled a corresponding one of the performance monitoring components; anda random access buffer memory having a plurality of memory locations, each of the plurality of memory locations corresponding to a corresponding one of the plurality of prescalers, the random access buffer memory separate from the local memory; and control logic coupled to the plurality of prescalers and to the random access buffer memory, the control logic configured to controllably transfer data from each of the plurality of prescalers to corresponding one of plurality of buffer memory locations, wherein the random access buffer memory comprises: a summing buffer comprising a plurality of summing buffer memory locations, each of the summing buffer memory locations corresponding to a corresponding one of the plurality of prescalers, the summing buffer configured to accumulate data from the plurality of prescalers; anda staging buffer comprising a plurality of staging buffer memory locations, each of the staging buffer memory locations corresponding to a corresponding one of the plurality of prescalers, the staging buffer configured to accumulate data from the plurality of prescalers and data from the summing buffer, and to provide that data to the processor, and wherein the prescalers buffer data between the plurality of performance monitoring components and the random access buffer memory.
地址 Milpitas CA US