Managing processor thread access to cache memory using lock attributes

摘要

Managing access to a cache memory includes dividing said cache memory into multiple of cache areas, each cache area having multiple entries; and providing at least one separate lock attribute for each cache area such that only a processor thread having possession of the lock attribute corresponding to a particular cache area can update that cache area.

主权项

1. A method of managing access to a cache memory, comprising:
dividing said cache memory into a plurality of cache areas, each said cache area comprising:
multiple entries, in which:
the multiple entries of a particular cache area share a plurality of identical bits at the beginning of a hash code corresponding to each entry; andeach entry comprises a keyword and a value associated with said keyword;anda representation of a data replacement order for a corresponding cache area; providing one separate lock attribute for each said cache area; maintaining a separate lock attribute for each said cache area; receiving a plurality of substantially concurrent requests to update a particular said cache area from a plurality of processor threads; granting possession of a said lock attribute corresponding to the particular said cache area to a selected said processor thread in said plurality of processor threads; allowing multiple processor threads to simultaneously possess separate lock attributes for separate cache areas; allowing said selected processor thread to update the particular said cache area only while said selected processor thread retains possession of said lock attribute corresponding to the particular said cache area, wherein updating said cache area comprises:
updating a data replacement order for said cache area by updating a physical arrangement of said multiple entries in said cache area; andupdating an entry in said cache area by updating at least one of said keyword and said value; and retracting possession of said lock attribute corresponding to the particular said cache area from said selected processor thread.