Apparatus and method for reducing the interface resistance in GaN Heterojunction FETs

摘要

The interface resistance between the source/drain and gate of an HFET may be significantly reduced by engineering the bandgap of the 2DEG outside a gate region such that the charge density is substantially increased. The resistance may be further reduced by using an n+GaN Cap layer over the channel layer and barrier layer such that a horizontal surface of the barrier layer beyond the gate region is covered by the n+GaN Cap layer. This technique is applicable to depletion and enhancement mode HFETs.

主权项

1. A method of reducing the interface resistance in an HFET device, the method comprising:
forming a device comprising a substrate, a channel layer, a barrier layer, a gate and a gate region; exposing a portion of the barrier layer in the gate region to form a ledge; forming a doped cap layer on the channel layer and the ledge of the barrier layer, wherein the doped cap layer is formed such that a downward projection of the doped cap layer would intersect with the ledge; forming a gate, source and drain on the device.