Methods and systems for pin-efficient memory controller interface using vector signaling codes for chip-to-chip communications

摘要

Systems and methods are described for transmitting data over physical channels to provide a high speed, low latency interface such as between a memory controller and memory devices. Controller-side and memory-side embodiments of such channel interfaces are disclosed which require a low pin count and have low power utilization. In some embodiments of the invention, different voltage, current, etc. levels are used for signaling and more than two levels may be used, such as a vector signaling code wherein each wire signal may take on one of four signal values.

主权项

1. A device comprising:
a link layer signaling protocol control circuit configured to receive a plurality of memory transaction signals from a bus controller and responsively generate link layer bits, at a link layer interface, representing the memory transaction signals as a message packet, wherein the message packet is selected from the group consisting of a memory write packet, a memo read packet and a status interrogation command packet; and, a physical layer signaling protocol control circuit connected to the link layer interface and configured to receive the link layer bits, select a set of data bits from the link layer bits, form a code word of a vector signaling code based on the selected set of data bits, the code word comprising a first set of symbols, map the first set of symbols of the code word to a collection of interconnection signal lines and synchronize symbol communication via symbol clock lines.