Gate driver and liquid crystal display including the same

摘要

A gate driver includes a gate integrated circuit (“IC”) chip which receives at least two scanning start signals and at least four clock control signals, and outputs a plurality of gate-on voltages, where at least two clock control signals of the at least four clock control signals are generated based on one scanning start signal of the at least two scanning start signals, timings of the at least two scanning start signals are independent of each other, and timings of the at least two clock control signals based on the one scanning start signal are independent of each other.

主权项

1. A liquid crystal display comprising:
a first pixel and a second pixel adjacent to each other in a column direction; and a gate integrated circuit chip which receives at least two scanning start signals and at least four clock control signals, and outputs a plurality of gate-on voltages, wherein the first pixel comprises:
a first switching element connected to a first gate line and a first data line;a second switching element connected to the first gate line and the first data line;a first subpixel electrode connected to the first switching element;a second subpixel electrode connected to the second switching element;a third switching element connected to the second subpixel electrode and a first charge sharing line; anda first capacitor connected to the third switching element, wherein the second pixel comprises:
a fourth switching element connected to a second gate line and a second data line;a fifth switching element connected to the second gate line and the second data line;a third subpixel electrode connected to the fourth switching element;a fourth subpixel electrode connected to the fifth switching element;a sixth switching element connected to the fourth subpixel electrode and a second charge sharing line; anda second capacitor connected to the sixth switching element, wherein at least two clock control signals of the at least four clock control signals are generated based on one scanning start signal of the at least two scanning start signals, wherein timings of the at least two scanning start signals are independent of each other, wherein timings of the at least two clock control signals based on the one scanning start signal are independent of each other, and the first gate line and the second gate line are applied with the gate-on voltage simultaneously.