Cost effective low pin/ball count level-shifter for LCD bias applications supporting charge sharing of gate lines with perfect waveform matching

摘要

A level shifter circuit has a plurality of channels for providing signals to a capacitive load and has circuits for sharing charge stored in the capacitive load between the channels. A first pair of channel clock generating circuits are coupled respectively to a first pair of channels. A second pair of channel clock generating circuits are coupled respectively to a second pair of channels. A pair of switches couple the first pair of channels together and the second pair of channels together, respectively, for sharing charge between the channels. A single resistor is coupled in circuit with all of the channels for controlling a slope of charge sharing between channels.

主权项

1. A level shifter for a liquid crystal display (LCD) comprising:
a first row line control circuit to control a first row line of the LCD; a second row line control circuit to control a second row line of the LCD; a third row line control circuit to control a third row line of the LCD; a fourth row line control circuit to control a fourth row line of the LCD; a first switch coupled to the first and the second row line control circuits for sharing charge stored on the first row line with the second row line; a second switch coupled to the third row line control circuit and the fourth row line control circuit for sharing charge stored on the third row line with the fourth row line; and a single resistor coupled between the first switch and the second row line control circuit and the single resistor coupled between the second switch and the fourth row line control circuit, wherein a slope of charge and discharge voltages on the row lines are substantially identical.