Method for forming a split-gate device

摘要

Forming a semiconductor device in an NVM region and in a logic region using a semiconductor substrate includes forming a dielectric layer and forming a first gate material layer over the dielectric layer. In the logic region, a high-k dielectric and a barrier layer are formed. A second gate material layer is formed over the barrier and the first material layer. Patterning results in gate-region fill material over the NVM region and a logic stack comprising a portion of the second gate material layer and a portion of the barrier layer in the logic region. An opening in the gate-region fill material leaves a select gate formed from a portion of the gate-region fill material adjacent to the opening. A control gate is formed in the opening over a charge storage layer. The portion of the second gate material layer is replaced with a metallic logic gate.

主权项

1. A method of forming a semiconductor device in an NVM (non-volatile memory) region and in a logic region using a semiconductor substrate, comprising:
forming a dielectric layer over the substrate in the NVM region and the logic region; forming a first gate material layer over the dielectric layer in the NVM region and the logic region; removing the dielectric layer and the first gate material layer from the logic region; forming, in the logic region, a high-k dielectric over the substrate and a barrier layer over the high-k dielectric; forming a second gate material layer over the barrier layer in the logic region and the first gate material layer in the NVM region; patterning the first gate material layer and the second gate material layer over the NVM region to form a gate-region fill material over the NVM region; patterning the second gate material layer and the barrier layer over the logic region to leave a logic stack comprising a portion of the second gate material layer and a portion of the barrier layer aligned to the portion of the second gate material layer over the logic region; forming an interlayer dielectric around the logic stack and around the gate-region fill material; and forming a control gate opening in the gate-region fill material to leave a select gate formed from a remaining portion of the gate-region fill material adjacent to the opening, wherein the opening has an exposed surface; forming a charge storage layer over the exposed surface; forming a control gate in the control gate opening over the charge storage layer; and replacing the portion of the second gate material layer with a metallic logic gate.