发明名称 Locking multiple voltage-controlled oscillators with a single phase-locked loop
摘要 Locking multiple VCOs to generate a plurality of LO frequencies, including: receiving a plurality of divided VCO feedback signals from a plurality of VCOs; receiving a reference signal multiplied by a predetermined number of the plurality of VCOs; generating and processing the predetermined number of phase differences between the multiplied reference signal and the plurality of divided VCO feedback signals in a single PLL circuit including a digital loop filter to receive and process the phase differences and generate (produce) a filter output, wherein the digital loop filter includes a plurality of delay cells equal to the predetermined number; and generating and outputting (delayed) control voltages for the plurality of VCOs based on the filter output.
申请公布号 US9252790(B2) 申请公布日期 2016.02.02
申请号 US201414251331 申请日期 2014.04.11
申请人 QUALCOMM INCORPORATED 发明人 Tang Yiwu;Park Jong Min;Sayilir Serkan;Narathong Chiewcharn
分类号 H03L7/099;H03L7/081 主分类号 H03L7/099
代理机构 Patterson & Sheridan, L.L.P. 代理人 Patterson & Sheridan, L.L.P.
主权项 1. A system including a phase-locked loop (PLL) circuit configured to lock multiple voltage-controlled oscillators (VCOs) for generating a plurality of local oscillator (LO) frequencies, the system comprising: a plurality of VCOs, each VCO generating an output signal of a particular frequency; a plurality of dividers, each divider configured to divide the output signal of a corresponding VCO, the plurality of dividers generating a plurality of divided VCO feedback signals; a phase-to-digital converter (PDC) configured to receive the plurality of divided VCO feedback signals from the plurality of dividers and a reference signal multiplied by a predetermined number indicating a number of the plurality of VCOs, and to generate the predetermined number of phase differences between the multiplied reference signal and the plurality of divided VCO feedback signals; a digital loop filter configured to receive and process the phase differences and generate a filter output, wherein the digital loop filter includes a plurality of delay cells equal to the predetermined number; and a digital-to-analog converter (DAC) configured to output control voltages for the plurality of VCOs based on the filter output.
地址 San Diego CA US