发明名称 Semiconductor package and method of fabricating the same
摘要 Provided are a semiconductor package and a method of fabricating the same. The package substrate includes a hole, which may be used to form a mold layer without any void. The mold layer may be partially removed to expose a lower conductive pattern. Accordingly, it is possible to improve routability of solder balls.
申请公布号 US9252095(B2) 申请公布日期 2016.02.02
申请号 US201313922722 申请日期 2013.06.20
申请人 Samsung Electronics Co., LTD. 发明人 Kim Jongkook;Park Su-min;Park Soojeoung;Baek Bona;Im Hohyeuk;Jang Byoungwook;Jung Yoonha
分类号 H01L23/498;H01L21/56;H01L23/00;H01L23/13;H01L25/065;H01L25/10;H01L23/31 主分类号 H01L23/498
代理机构 Harness, Dickey & Pierce 代理人 Harness, Dickey & Pierce
主权项 1. A semiconductor package, comprising: a package substrate including at least one non-metallized hole; at least one lower conductive pattern on a bottom surface of the package substrate; at least one semiconductor chip mounted on the package substrate in a flip-chip bonding manner; and a mold layer on the package substrate, the mold layer including, an upper mold portion covering the at least one semiconductor chip and a top surface of the package substrate, a lower mold portion including a first mold side surface and connected to the upper mold portion through the at least one non-metallized hole to cover at least a portion of the bottom surface of the package substrate and expose at least a portion of the lower conductive pattern, and the lower mold portion including a mold bottom surface defining a lower mold hole exposing the at least one portion of the lower conductive pattern; and at least one lower solder ball on the lower conductive pattern, the at least one lower solder ball being in direct contact with the first mold side surface.
地址 Gyeonggi-do KR