Non-volatile memory with silicided bit line contacts

摘要

An approach to use silicided bit line contacts that do not short to the underlying substrate in memory devices. The approach provides for silicide formation in the bit line contact area, using a process that benefits from being self-aligned to the oxide-nitride-oxide (ONO) nitride edges. A further benefit of the approach is that the bit line contact implant and rapid temperature anneal process can be eliminated. This approach is applicable to embedded flash, integrating high density devices and advanced logic processes.

主权项

1. A method comprising:
disposing a first dielectric layer on a substrate; disposing a dielectric charge trapping layer on the first dielectric layer; disposing a second dielectric layer on the dielectric trapping layer; patterning a hard mask on the second dielectric layer; disposing an oxide spacer on sidewalls of the hard mask to leave exposed a bit line contact region; removing portions of the second dielectric layer, dielectric trapping layer and first dielectric layer within the bit line contact region; removing portions of the oxide spacer to leave exposed a portion of the second dielectric layer; and removing the exposed portion of the second dielectric layer to thereby yield extended portions of the dielectric trapping layer and first dielectric layer.