| 摘要 |
PROBLEM TO BE SOLVED: To solve problems that: in an optical lithography process, as correction to dimension change due to etching, an etching bias is added according to a gap between an object mask pattern and a proximate mask pattern; but, when the object pattern is a gate electrode, when a proximate pattern is arranged in the vicinity of a boundary of an active area, a bias start point is set inside the active area; and at the time, a step is formed on a contour of the mask pattern, and during exposure, an effect of rounding from the step spreads to the active area, resulting in variation of the gate dimension.SOLUTION: The summary of the present invention relates to a lithography step or the like in a production process of a semiconductor integrated circuit device, in which, when data on an optical mask used in gate electrode patterning is created, in a certain range from the boundary of the active area, a bias correction step is prevented from occurring on a gate electrode pattern on which etching bias correction is performed.SELECTED DRAWING: Figure 8 |
