| 摘要 |
<p>The present invention relates to a circuit (40) for generating at least two rectangular signals (S1, S2) with adjustable phase shift comprising a frequency divider circuit (46) receiving a clock signal (CLK) as input and supplying a signal (CLK_2) as output, at least two comparators (C1, C2), respectively receiving a first threshold voltage (Vs1) and at least one second threshold voltage (Vs2) on one input, and a ramp signal synchronised with the clock signal on a second input, the at least two threshold voltages making it possible to adjust the value of the phase shift between the at least two rectangular signals and at least two D-type switches (D1, D2) respectively receiving the output signal (Cmp1) from the first comparator and the output signal (Cmp2) from the second comparator on the clock inputs thereof, and the output signal of the frequency divider circuit on the "D" input thereof.</p> |
